Switching Circuit Arrangement

ABSTRACT

A switching circuit arrangement is disclosed. The arrangement includes a substrate, a plurality of functional units arranged on the substrate, a plurality of selection line groups including selection lines, a plurality of signal line groups including signal lines, a buffer unit for each signal line group, a selection unit which is coupled to the selection line groups, and a signal unit which is coupled to the signal lines.

PRIORITY STATEMENT

This application is the national phase under 35 U.S.C. § 371 of PCTInternational Application No. PCT/DE2005/000876 which has anInternational filing date of May 12, 2005, which designated the UnitedStates of America and which claims priority on German Patent Applicationnumber DE 10 2004 023 855.3 filed May 13, 2004, the entire contents ofwhich are hereby incorporated herein by reference.

FIELD

The invention generally relates to a circuit arrangement.

BACKGROUND

In sensor arrays, sensor elements of the same or even different type areoften arranged in an array, for example in the form of a matrix. Sucharrangements, unlike individual sensors, enable important additionalinformation to be found, such as the spatial resolution of sensorevents. Such arrangements also allow sensor processes to run in parallelin time.

In order to read out the signal from a sensor element in an array, thesensor element is often connected to interface circuits and devices.Often it is not possible from a technical perspective or not practicaleconomically to connect each individual sensor element individually i.e.to wire them up to the interface circuits using lines separatelyallocated to each individual sensor element.

Employing a switching matrix using row lines and column lines that areselected by row and column decoders, each row line or column line beingassigned to a plurality of sensor elements in common, enables one or atleast a reduced number of signal lines to be shared for the outputsignals of the individual sensors, by which the sensor array transfersthe data from the sensor elements to the interface circuits. Such awiring architecture means that certain constraints must be observed whenreading out a sensor array.

A sensor arrangement known in the prior art is described below withreference to FIG. 1A.

In the sensor arrangement 100 of FIG. 1A, a plurality of sensor elements102 is arranged in the form of a matrix on a substrate 101. Each sensorelement 102 is connected to a row line 103 and to a column line 104, acommon row line 103 being provided for each of sensor elements 102 of arow, and a common column line 104 being provided for each of sensorelements 102 of a column. The row lines 103 are connected to a rowdecoder 105, whilst the column lines 104 are connected to a columndecoder 106.

As shown in the magnified view of individual sensor elements 102 in FIG.1A, by applying a suitable signal to the row line 103 pertaining to aspecific sensor element 102, a switch element 110 of a sensor element102 to be selected is closed, whereby the sensor field 109 (for instancea sensor electrode at which sensor events can take place) pertaining tothe sensor element 102 to be selected is connected to the associatedcolumn line 104. A sensor element selected in this way can then beconnected to the electronic interface circuit 107 if the selectionswitch 111 contained in the column decoder 106 has a suitable switchsetting, whereby the sensor signal from the selected sensor element 102is provided at an output of the electronic interface circuit. The rowdecoder 105 and the column decoder 106 are given the address of a sensorelement 102 to be selected by an address generator 108.

The sensor arrangement 100 of FIG. 1A is a 4×4 sensor array. A sensorelement 102 of the sensor arrangement 100 is selected by providing thecolumn decoder 105 and the row decoder 106 with such control signalsthat a specific sensor element 102 a can be selected. The sensor element102 at the intersection of an enabled column and row is the selectedsensor element 102 a. To read out its sensor signal, this selectedsensor element 102 a is connected to the electronic interface circuit107.

A sensor arrangement 150 according to the prior art is described belowwith reference to FIG. 1B, in which are shown details of the electronicinterface circuit 107 of FIG. 1A.

The selection switch 111 is connected to an input of a first amplifier151, which has a first and a second output. The first output of thefirst amplifier is connected to a first input of a comparator 153, whosesecond input is connected to a reference current source 152. The secondoutput of the first amplifier 151 is connected to an input of a secondamplifier 154. The second amplifier 154 is controlled by a controlsignal supplied by an output of the comparator 153. In addition, anoutput of the second amplifier 154 is connected to an input of ananalog-to-digital converter 155, whose output, like the output of thecomparator 153, is connected to an output unit 156.

The “frame frequency” is the definitive measure of the achievabletemporal resolution that a sensor arrangement 100 or a sensorarrangement 150 can deliver. The frame frequency is obtained from thetime required to read out the whole sensor arrangement once in full. The“pixel frequency” is the crucial factor here. It is given by the timerequired to read out a single sensor element 102. Thus, for the arrayarchitecture of FIG. 1A, the frame frequency is obtained from thequotient of the pixel frequency and the number of sensor elements 102 ofthe sensor arrangement 100.

For a constant pixel frequency, the frame frequency is inverselyproportional to the number of sensor elements 102. Thus for a largesensor arrangement 100 having a large number of sensor elements 102,only a slower read-out is possible if the pixel frequency cannot beincreased correspondingly.

The transient response times of a sensor element 102 and of theelectronic interface circuit 107 after selecting a sensor element 102 alimit the pixel frequency. These transient response times are usuallyinversely proportional to the size of the sensor signal, so that forsmall signal amplitudes the transient response times are often verylong. A large dynamic range of a sensor, i.e. the range of signalamplitudes to be covered, can also result in long transient responsetimes, in particular in the interface circuits 107, because theoperating point must vary within a large range.

The interrelationships described can hence lead to an unsatisfactoryread-out speed, in particular for a sensor arrangement 100 containing alarge number of sensor elements 102 that are to supply a signal over alarge dynamic range. This problem is further aggravated when the dynamicrange is also to contain very small signal amplitudes in particular.

An electronic DNA sensor array is disclosed in [1].

A sensor arrangement is disclosed in [2], in which the sensor devicesare calibrated column by column before the actual measurement. A columnto be calibrated is selected by applying a control signal having thelogic value “1” to a selection terminal, and a sensor device of thecorresponding column is calibrated using a read-out or calibrationcircuit and a selector-switch element, which is switched such that aconstant current is injected into the sensor device to be calibrated. Inaddition, to calibrate the sensor devices of a column, a control signalhaving the logic value “1” is briefly applied to a calibration terminalof the corresponding column. During the measurement, a column isselected by a selection terminal, and a sensor device of thecorresponding column is read out using the aforementioned read-out orcalibration circuit and the aforementioned selector-switch element,which is switched such that a constant voltage is applied to the sensordevice to be read out.

A sensor array is described in [3], in which a plurality of sensorcells, which can be connected to row lines and column lines, arearranged on a substrate. Both the row lines and the column lines can beconnected to at least two of the sensor cells in each case.

The sensor cells can be selected individually using a row-selectionregister and a column-selection register. In addition, the arrangementdescribed in [3] includes a multiplexing and amplification circuitconnected to the sensor cells, which is controlled by a secondcolumn-selection register. By way of the multiplexing and amplificationcircuit and the second column-selection register, the output signals ofindividual sensor cells are amplified and provided sequentially as theoutput signal from the sensor array.

A sensor arrangement is disclosed in [4], in which the individualsensors are provided, before the measurement, with a potential lyingclose to the measured value of the sensor element to be read out.

A sensor array is described in [5], in which initially the operatingpoint of a sensor element is set via a switch during a set-up phasepreceding a measurement phase, and afterwards the sensor element is readout via a different switch.

SUMMARY

At least one embodiment of the invention is based in particular on theproblem of creating a circuit arrangement in which a signal transferbetween a plurality of functional units and an electronic interfacecircuit can take place with sufficient speed.

The problem is solved by a circuit arrangement having the features givenin at least one embodiment of the invention.

The circuit arrangement according to at least one embodiment of theinvention comprises a substrate, a plurality of functional unitsarranged on the substrate and a plurality of selection-line groups, eachselection-line group having at least two selection lines, each of whichcan be connected to at least two of the functional units. In addition, aplurality of signal-line groups is provided, each signal-line grouphaving at least two signal lines, each of which can be connected to atleast two of the functional units. A buffer unit is provided for eachsignal-line group.

In addition, a selection unit connected to the selection-line groups isprovided, which is configured such that by applying a selection signalto the selection lines of a selection-line group to be selected, thefunctional units connected to the selection lines of the selectedselection-line group are connected to the associated signal lines.

The circuit arrangement also contains a signal unit connected to thesignal lines, which is configured such that it selects one, and onlyone, of the signal-line groups at a time in such a way that, of thosefunctional units that belong both to the selected selection-line groupand to the selected signal-line group, one, and only one, functionalunit is selected at a time for signal transfer between this functionalunit and the signal unit. The signal unit is also configured such that,of those functional units that belong both to the selectedselection-line group and to an unselected signal-line group, it connectsone, and only one, functional unit at a time to the associated bufferunit, thereby allowing this functional unit to settle.

At least one embodiment of the invention is based on performing a signaltransfer between a selected functional unit and a signal unit, in acircuit arrangement having a plurality of functional units, in a mannerthat is faster compared with the prior art, by advancing in time thetransient behavior—which reduces the pixel frequency—of a respectivefunctional unit with respect to the actual signal transfer between thefunctional unit and the signal unit. In other words, those functionalunits that are intended for signal transfer in the relatively nearfuture, are already connected to a buffer unit during the signaltransfer of other functional units, so that the functional units due forimminent signal transfer can already settle.

If the signal transfer of the functional unit that is ahead in time thenfinishes, and the signal transfer of the functional unit that hasmeanwhile already at least partially settled into a steady state,begins, then the effective signal transfer time, composed of thetransient response time and actual signal transfer time, for thefunctional unit now undergoing a signal transfer, is reduced by theadvanced (already fully or partially elapsed) transient response time.

Signals are transferred between the functional units and the signalunit. When the circuit arrangement is configured as a sensorarrangement, sensor signals from the functional units formed as sensorelements are read out to a signal processing unit for example. For acircuit arrangement configured as a display unit, the functional unitsimplemented as display pixels are supplied by a supply unit, forexample, such that the pixels are provided with the information thatthey require to display the pixel information. The circuit arrangementis not restricted to the two implementations as sensor arrangement ordisplay unit described, but rather the architecture of the circuitarrangement according to at least one embodiment of the invention can beused for any arrangement having a plurality of functional units that aresupplied with signals or from which signals are taken.

The circuit arrangement of at least one embodiment of the invention, inparticular in its embodiment as sensor arrangement, is suitable forreading out sensor signals even of low amplitude and large dynamic rangeat sufficiently high speed even for sensor arrangements having a largenumber of sensor elements.

An important aspect of at least one embodiment of the invention is thattransient response times of functional units in a data path of a circuitarrangement having a plurality of functional units, in particular sensorelements of a sensor arrangement, are ostensibly concealed by means of asuitable array architecture, and hence the potential read-out speed ofthe sensor array is increased. A sensor element for later read-out isalready selected in advance, so that up to the time at which itsread-out starts, it can go through, and preferably also complete by thestart of its read-out, its transient behavior.

The read-out time of a sensor element is then only given by the actualdata transfer time, whilst the transient response time shifted inadvance of the data transfer is eliminated. In other words, thefunctional units are brought into a steady state in a process stepadvanced with respect to the actual read-out, from which state theactual read-out can then proceed without delay.

A fundamental idea of at least one embodiment of the invention for theembodiment of the circuit arrangement as a sensor arrangement resides inincreasing the pixel frequency by effectively concealing transientbehavior in time. The problem occurring in the prior art of too low aread-out speed is thereby solved or at least greatly reduced.

The following signal-transfer strategy is preferably implemented:

1) The sequential signal-transfer process (e.g. read-out) between thefunctional units (e.g. sensor fields) and the signal unit of the circuitarrangement (e.g. sensor arrangement) cannot be randomly selected but ispre-defined (for example in order of increasing addresses, row by row).

2) The functional units implemented according to the prior art in asingle signal line (e.g. column line) are implemented in two or more newsub-signal lines (e.g. sub-column lines). Such sub-signal lines aregrouped into signal-line groups.

3) Two or more selection lines (e.g. row lines) are selectedsimultaneously (e.g. by means of a row decoder) or grouped into aselection-line group. In other words, simultaneously selectedselection-lines are grouped into selection-line groups. A selectedselection-line (e.g. row line) can be connected exclusively tofunctional units of a sub-signal line. At a specific time, just onespecific functional unit that is assigned both to a selectedselection-line group and to a selected signal-line group is read out.Those functional units implemented as sensor elements that are intendedto be read out in subsequent cycles and belong both to a selectedselection-line group and to an unselected signal-line group, areconnected to an associated buffer unit, so that they can already gothrough transient behavior, preferably over a plurality of signaltransfer cycles (e.g. read-out cycles) of functional units (e.g. sensorelements) that are advanced in time.

4) An additional pre-decoder, having buffers connected downstream, isprovided in the read-out path.

Sensors belonging to one of the at least two selected selection-lines(row lines) are then either connected to the full data path or to abuffer unit. In other words, those sensors of the selected selectionlines that are not already being read out at a certain time are able tosettle in this period. The time gained as a result of this leads to anincreased pixel frequency and hence frame frequency, and enables fasterread-out of the circuit arrangement according to at least one embodimentof the invention.

Preferred developments of the invention follow from the exampleembodiments.

In at least one embodiment, each selection-line group includes, forexample, exactly two selection lines. In addition, in at least oneembodiment each signal-line group includes, for example exactly twosignal lines.

In at least one embodiment, the circuit arrangement is, for example,configured as a monolithically integrated circuit arrangement. If thecircuit arrangement is provided in a monolithically integrated form, inparticular formed in a semiconductor substrate (e.g. silicon wafer,silicon chip), a miniaturized implementation of the circuit arrangementis possible. The circuit arrangement can be fabricated usingstraightforward engineering by the sophisticated processes of siliconmicroelectronics. In addition, in an integrated implementation of thecircuit arrangement, signal paths are short and hence the achievableread-out times are low. Furthermore, an excellent spatial resolution ispossible because the functional units can be scaled in the micrometerand sub-micrometer range.

The functional units may be sensor fields and configured such that byway of signal transfer between the currently selected functional unitand the signal unit, a sensor signal can be read out from the selectedfunctional unit implemented as a sensor field.

According to this embodiment, the circuit arrangement is implemented asa sensor arrangement, in which a plurality of sensor fields arepreferably arranged in the form of a matrix, with sensor signals beingread out from the sensor fields according to the architecture accordingto at least one embodiment of the invention, which results in a fasterread-out capability owing to the elimination of, or reduction in,transient behavior. The temporal resolution of the circuit arrangementimplemented as a sensor arrangement can thereby be improved.

In at least one embodiment, the circuit arrangement is preferablyimplemented as a biosensor arrangement. For example, a plurality ofnerve cells can be grown on the surface of the biosensor arrangement,and the electrical impulses from the nerve cells can be detected bybiosensors. Alternatively, capture molecules can be immobilized on thesensor fields of the circuit arrangement configured as a biosensorarrangement, which can hybridize with macromolecular biopolymers in ananalyte to be examined. Hybridization events can then be detectedelectrically and/or optically, for example, by way of a sensor signal.Such a biosensor arrangement is particularly advantageous in the area ofhigh-throughput screening.

The functional units may be memory cells and be configured such that viasignal transfer between the currently selected functional unit and thesignal unit, an information signal can be read out from the selectedfunctional unit configured as a memory cell. In this embodiment, eachfunctional unit is a memory cell, for example a DRAM memory cell or anEPROM memory cell. When reading out the memory contents from the memorycells, transient behavior of the individual memory cells also results inan increase in the read-out time and hence to poorer access times.According to at least one embodiment of the invention, the read-out timeis cut and the access time reduced by transient behavior being conductedbefore the actual read-out process, and the individual memory cellsbeing already in a state ready for read-out, i.e. in, or at leastapproaching, a steady state, at the start of a read-out cycle.

It should also be mentioned that, in an embodiment of the circuitarrangement as a memory-cell arrangement, the programming of the memorycells, i.e. a signal transfer from a control unit to the memory cells,can also be executed in a faster manner because transient behaviorduring programming of the memory cells can also be effectivelyeliminated or reduced by completing the transient behavior prior to theactual storage operation with no impact on the functionality of the restof the programming.

The functional units may alternatively be playback fields, and may beconfigured such that by means of signal transfer between the currentlyselected functional unit and the signal unit, a playback signal isprovided from the selected functional unit configured as a playbackfield.

In this embodiment of the functional units as playback fields, thecircuit arrangement is a display device for example, for instance an LCDdevice or another display device containing pixel elements. The playbackof optically perceptible or other information on the circuit arrangementcan be performed more quickly by means of the principle according to atleast one embodiment of the invention, so that the frequency at whichthe new images are built up on the display unit is increased.

The circuit arrangement can thus be configured as a display arrangement.

In addition, in at least one embodiment the circuit arrangement maycomprise an amplifier unit, which is configured to amplify a signalprovided by the selected functional unit of the signal unit. Inparticular, in an implementation of the circuit arrangement forbiosensor applications, the signals obtained are often very small inamplitude and are preferably amplified before being supplied to anexternal electronic signal processing circuit.

The circuit arrangement can comprise a signal processing sub-circuit forprocessing a signal to be transferred, where the signal processingsub-circuit may be contained at least partially in a respective bufferunit of a respective signal-line group. According to this embodiment,some of the components (e.g. amplifier, comparator, analog-to-digitalconverter, reference current source etc.) of an electronic interfacecircuit may be integrated in each of the buffer units (or some of them).This has the advantage that while a functional unit is settling, it isalready connected to the components of the signal processing sub-circuitthat are contained in the buffer unit, so that the transient responsetime of these components can also be advanced in time with respect tothe actual signal transfer. This results in a further increase in theread-out rate.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments of the invention are shown in the figures, andexplained in more detail below, in which:

FIG. 1A shows a sensor arrangement according to the prior art,

FIG. 1B shows another sensor arrangement according to the prior art,

FIGS. 2A, 2B show schematic diagrams that are used to explain one aspectof the invention,

FIG. 3A shows a sensor arrangement according to a first exampleembodiment of the invention in a first operating state,

FIG. 3B shows the sensor arrangement according to the first exampleembodiment of the invention in a second operating state,

FIG. 4 shows a detailed view of a signal unit of the circuit arrangementaccording to the invention according to an example embodiment of theinvention,

FIGS. 5 and 6 show schematic diagrams that are used to explain howsensor elements are read out according to an example embodiment of theinvention,

FIG. 7 shows a schematic view of a circuit arrangement configured as abiosensor arrangement according to a second example embodiment of theinvention,

FIG. 8 shows a sensor arrangement according to a third exampleembodiment of the invention,

FIG. 9 shows a sensor arrangement according to a fourth exampleembodiment of the invention,

FIG. 10 shows a sensor arrangement according to a fifth exampleembodiment of the invention.

Identical or similar components in different figures are given the samereference numerals.

The diagrams in the figures are schematic and not to scale.

DETAILED DESCRIPTION OF THE EXAMPLE EMBODIMENTS

A fundamental idea of the circuit arrangement according to an exampleembodiment of the invention is described below with reference to FIG.2A, FIG. 2B.

FIG. 2A shows the principle of reading out sensor elements of a sensorarrangement according to the prior art. It shows a column line 104having a plurality of sensor elements 102 and a selected sensor element102 a. In addition, it shows row lines 103. The selected sensor element102 a is arranged in an intersection area of a selected row line 103 andthe selected column line 104, with a sensor signal from the selectedsensor element 102 a being supplied to the column decoder 106. If thesensor element 102 a is selected, then prior to the actual read-outprocess, i.e. the signal transfer to the column decoder 106, theselected sensor element 102 a must go through transient behavior untilit is brought into a state that is sufficiently steady for the read-out.Thus the pixel frequency is low and read-out is slow.

FIG. 2B shows schematically the implementation according to an exampleembodiment of the invention. It shows a plurality of sensor elements200, where each sensor element 200 is connected to an associated rowline 201 and an associated column line 202.

According to an example embodiment of the invention, a single row lineis not now selected, as in FIG. 2A, but two row lines 201 (also calledselection lines) of a selected selection-line group 203. In addition,unlike FIG. 2A, a single column line 202 is not selected in FIG. 2B, buttwo column lines 202 (also called signal lines) assigned to a selectedsignal-line group 204.

A selected sensor element 200 a is due for imminent read-out. Thisselected sensor element 202 a due for imminent read-out belongs both tothe selected selection-line group 203 and to the selected signal-linegroup 204. A switch element 207 of a pre-decoder 205 is switched suchthat the sensor element 200 a selected for imminent read-out isconnected to a buffer unit 206. Thus in the operating state shown inFIG. 2B, the selected sensor field 200 a has already started transientbehavior before the actual read-out process takes place.

If the selected selection-line group 203 and the selected signal-linegroup 204 is adjusted in such a way, and the electronic interfacecircuit (not shown in FIG. 2B) is switched in such a way that now theselected and settled sensor element 200 a is to release its sensorsignal for read-out to the electronic interface circuit, then a read-outtime is achieved for this actual read-out that is reduced by thetransient response time compared with FIG. 2A. Hence according to FIG.2B it is possible to read out the sensor elements 200 more quicklybecause of the increased pixel frequency.

A sensor arrangement 300 according to a first example embodiment of theinvention is described below with reference to FIG. 3A, where the sensorarrangement 300 in FIG. 3A is shown in a first operating state.

The sensor arrangement 300 is monolithically integrated in a siliconsubstrate 301. The sensor arrangement 300 includes a plurality of sensorelements 302 arranged on the silicon substrate 301. In addition, aplurality of selection-line groups are provided, each selection-linegroup including at least two of a plurality of selection lines 303 (rowlines in FIG. 3A), each of which is connected to four of the sensorelements 302. In addition, a plurality of signal-line groups areprovided, each signal-line group comprising two signal lines 305 (columnlines in FIG. 3A), each of which is connected to two of the sensorelements 302. Each signal-line group is assigned a buffer unit 307.

In addition, a selection unit 308 connected to the selection-line groupsis shown, which is configured such that by means of a selection signalon the selection lines 303 of a selection-line group 304 to be selected,the sensor elements 302 connected to the selection lines 303 of theselected selection-line group 304 are connected to the associated signallines 305 (as shown in the magnified diagrams of FIG. 1A). Furthermore,the sensor arrangement 300 contains a signal unit 309 connected to thesignal lines 305.

The signal unit 309 is configured in such a way that it selects one, andonly one, of the signal-line groups 306 at a time in such a way that, ofthose sensor elements 302 that belong both to the selectedselection-line group 304 and to the selected signal-line group 306, one,and only one, read-selected sensor element 302 b at a time is selectedfor signal transfer between this read-selected sensor element 302 b andthe signal unit 309. In addition, the signal unit 309 is configured suchthat, of those sensor elements 302 that belong both to the selectedselection-line group 304 and to an unselected signal-line group, itconnects one, and only one, settling-selected sensor element 302 a at atime to the associated buffer unit 307, thereby allowing thissettling-selected sensor element 302 a to settle.

The signal unit 309 and the selection unit 308 are provided by anaddress generator 314 with selection signals for addressing the sensorelements 302.

The signal unit 309 is composed of a pre-decoder 310 having first switchelements 311, the buffer units 307 and the signal decoder 312. Thesignal decoder 312 is connected on its output side to an electronicinterface circuit 313, which is configured to post-amplify a sensorsignal read out from a read-selected sensor element 302 b.

The way in which the sensor arrangement 300 works is described in moredetail below. The sensor arrangement 300 is a 4×4 sensor array, whereFIG. 3A shows a first operating state of the sensor arrangement 300. Therow lines 303 addressed by the selection unit 308, which may also becalled a row decoder, are those assigned to the selected selection-linegroup 304. The sensor element currently being read out is called theread-selected sensor element 302 b. In the operating state shown in FIG.3A, the sensor elements 302 of the upper selected row line 303 shown inFIG. 3A are read out sequentially.

At the end of each read-out operation, which corresponds to the start ofthe read-out operation of the sensor signal from the next sensor elementin line, the relevant switch elements 311 of the pre-decoder 310 areswitched over. As a result of this, a sensor element of the lowerselected selection line 303 shown in FIG. 3A is switched to theassociated buffer 307 and can start to settle.

In FIG. 3A, those sensor elements that have already started the settlingprocess and are due for read-out in forthcoming read-out cycles, arecalled settling-selected sensor elements 302 a. The numbers in thesettling-selected sensor elements 302 a in FIG. 3A represent the time,in units of the reciprocal of the pixel frequency, that the respectivesettling-selected sensor element 302 a has already been settling for.The read-selected sensor element 302 b connected to the data path311-307-315-313 here has had the longest time period available forsettling (four time units).

The next sensor element due for read-out has accordingly spent thesecond longest time period in settling, namely three time units. At thispoint in time, the last settling-selected sensor element 302 a to beread out has been settling for the period of one reciprocal of the pixelfrequency. Once all the sensor elements of the upper selected selectionline 303 have been read out, the sensor elements of the lower selectedselection line 303 shown in FIG. 3A of the selected selection-line group304 are then read out. In addition, the previously upper selectedselection line 303 is deselected, and instead an additional newselection line 304 is addressed by the selection unit 308.

A second operating state of the sensor arrangement 300 shown in FIG. 3Ais described below with reference to FIG. 3B.

In the second operating state shown in FIG. 3B, the same selection lines303, and hence the same selection-line group 304, as in FIG. 3A arestill selected. Now, however, the pair of signal lines 305, that isassigned to the signal-line group 306 now selected, is shifted onecolumn to the right as shown in FIG. 3B.

According to the operating state of FIG. 3B, the sensor signal from thenow read-selected sensor element 302 b is now read out, which accordingto the operating state of FIG. 3A was the settling-selected sensorelement 302 a, which had already been settling for three time units inthe operating state of FIG. 3A. In addition, that sensor element of thesensor elements 302 that in FIG. 3A lies in the same selection line asthe settling-selected sensor element 302 a labeled with the time unit“1” in FIG. 3A, but shifted one position to the right, is now alsoselected for settling.

It is apparent that, as shown in the transition from FIG. 3A to FIG. 3B,the settling-selected and read-selected sensor elements 302 a, 302 b areshifted successively from left to right. After such a shift cycle iscomplete, a new pair of selection lines 303 is selected to form theselected selection-line group 304.

A detailed view of an embodiment of the signal unit 309 in circuitry isdescribed below with reference to FIG. 4.

A function block 400 is provided in the signal unit 309 for each groupof two signal lines 305. The function blocks 400 each have essentiallythe same design, so that the detailed design of the function block 400is only described for the left-hand pair of signal lines 305 shown inFIG. 4.

The pair of signal lines 305 assigned to the function block 400comprises a first signal line 401 a and a second signal line 401 b. Thefirst signal line 401 a is connected to a first source/drain region of afirst switching transistor 402. The second source/drain region of thefirst switching transistor 402 is connected to a first source/drainregion of a second switching transistor 403, whose second source/drainterminal is connected to the second signal line 401 b. The secondsource/drain region of the first switching transistor 402 and the firstsource/drain region of the second switching transistor 403 are connectedto an input of the buffer 307 assigned to the signal lines 401 a, 401 b.The output of the buffer 307 is connected to a first source/drain regionof a third switching transistor 404. The second source/drain region ofthe third switching transistor 404 is connected to the electronicinterface circuit 313, which is only indicated schematically in FIG. 4.

A common pointer circuit 405 is provided for all the function blocks400, which is supplied with a clock signal CLK at an input 406. Anoutput 407 of the pointer circuit 405 is connected to the gate region ofthe third switching transistor 404 and to a first input of a flip-flop408. A first output of the flip-flop 408 is connected to the gateterminal of the first switching transistor 402. In addition, a secondoutput of the flip-flop 408 is connected to the gate terminal of thesecond switching transistor 403, to a second input of the flip-flop 408and to a first source/drain terminal of a fourth switching transistor409. The second source/drain terminal of the fourth switching transistor409 is taken to the electrical ground potential 410. The gate terminalof the fourth switching transistor 409 can be controlled by a signalINIT.

The operation of the circuit implementation of the signal unit 309 shownin FIG. 4 is described below.

FIG. 4 shows an example of the implementation of the pre-decoder 310 andthe signal decoder 312 of the sensor arrangement 300. The clock signalCLK gates the pointer circuit 405 so that all column addresses (i.e.addresses of the signal lines 305) are selected successively. With everychange in a column 305, the falling edge of the pointer-circuitoutput-signals that gate the switching transistors (active high in theexample) is detected in the toggle flip-flop 408 in the pre-decoder 310,and is used to switch the sub-columns 305. The two states of the toggleflip-flop 408 correspond to selecting a sub-column (sub-signal-line)that is linked to a row or selection line having an odd or even address.All the toggle flip-flops 408 of all function blocks 400 can be set intoa defined initial state using the control signal INIT, so that thesensor addressing is explicit.

In the explained example, the buffer units 307 are located betweenpre-decoder 310 and signal decoder 312. Hence it is possible to reducethe limiting effect that the transient response time of the sensorelements 302 has on the pixel frequency.

The transient response times in the interface circuits 313 in thedownstream data path are often important as well. In order to increasethe pixel frequency further, it is possible in principle to shift thefunctions of these interface circuits 313, at least partially (forexample the signal amplification components) into a stage betweenpre-decoder 310 and signal decoder 312. Such an implementation involvesbalancing the increase in read-out speed with the surface area required.

The advantage of the architecture according to an example embodiment ofthe invention with regard to scaled arrays is explained again below withreference to the schematic diagram of FIG. 5, FIG. 6.

FIG. 5 shows schematically the principle that can be applied to increasethe pixel frequency by way of the settling being advanced according tothe invention with respect to the actual read-out of a sensor element,i.e. by effectively eliminating the transient response time to.

FIG. 5 shows schematically the achievable read-out time for aconventional implementation 500 of a sensor arrangement compared withthe implementation 501 according to an example embodiment of theinvention. In the conventional implementation, the read-out timet_(pixel) for reading out one pixel is the reciprocal of the pixelfrequency f_(Pixel), and is made up of the transient response time andthe actual read-out time.

In contrast, the time t_(pixel) _(—) _(new) required according to anexample embodiment of the invention to read out one pixel is reducedcompared with t_(pixel) by the transient response time t₀ that a sensorelement connected to a read-out path needs to reach a steady state. Suchtransient behavior is advanced in time according to an exampleembodiment of the invention with respect to the actual read-out of asensor field.

The following relationship applies in FIG. 5:

$\begin{matrix}{t_{Pixel} = {\frac{1}{f_{Pixel}} = {t_{0} + t_{Pixel\_ new}}}} & (1)\end{matrix}$

The maximum possible time to that can be saved by way of the strategyaccording to an example embodiment of the invention when reading out apixel depends on the number of columns #_(c) in the sensor arrangement:

t ₀=(#_(c)−1)t _(Pixel) _(—) _(new)  (2)

The pixel frequency f_(Pixel) _(—) _(new) of the strategy according toan example embodiment of the invention is obtained from equations (1)and (2) as:

F _(Pixel) _(—) _(new)=#_(C) f _(Pixel)  (3)

Using the nomenclature of FIG. 5, FIG. 6, the frame frequency for thetraditional strategy 500, f_(Frame), and for the strategy 501 accordingto the invention, f_(Frame) _(—) _(new), for a circuit arrangement of acertain geometry and of a scaled version of this circuit arrangement isgiven by:

$\begin{matrix}{f_{Frame} = {\frac{f_{Pixel}}{N} = \frac{f_{Pixel}}{\#_{C}\#_{R}}}} & (4) \\{f_{Frame\_ new} = {\frac{f_{Pixel}}{\#_{R}} = {\#_{C}f_{Frame}}}} & (5) \\{f_{Frame}^{*} = {\frac{f_{Pixel}}{s^{2}N} = \frac{f_{Frame}}{s^{2}}}} & (6) \\{f_{Frame\_ new}^{*} = {\frac{\#_{C}}{s}f_{Frame}}} & (7)\end{matrix}$

where N is the number of positions of a sensor arrangement and #_(R) isthe number of rows. In addition, s#_(C) is the number of columns of ascaled sensor arrangement for a scaling factor s, and S#_(R) is thenumber of rows of the scaled sensor arrangement. Furthermore, N*=Ns² isthe number of positions in the scaled sensor arrangement, f*_(Pixel) isthe pixel frequency in a conventional scaled sensor arrangement,f*_(Frame) is the frame frequency in a conventional scaled sensorarrangement, f*_(Pixel) _(—) _(new) is the pixel frequency in a scaledsensor arrangement according to the invention, f*_(Frame) _(—) _(new) isthe frame frequency in a scaled sensor arrangement according to anexample embodiment of the invention.

Table 1 summarizes the calculated values for the conventional strategy500 and for the strategy 501 according to an example embodiment of theinvention. It can be seen from table 1 that using the strategy accordingto an example embodiment of the invention, a reduction in the arrayread-out speed when the number of columns and rows are scaled by afactor of s respectively can be compensated by the number of columns#_(C).

TABLE 1 Number of sensor Pixel Frame Array architecture elementsfrequency frequency Conventional Array N F_(Pixel) f_(Frame) Scaled s²NF_(Pixel) s⁻²f_(Frame) array According to Array N #_(c) f_(Pixel) #_(c)f_(Frame) an example Scaled s²N s #_(c) f_(Pixel) s⁻¹ #_(c) f_(Frame)embodiment array of the invention

To summarize, FIG. 5 illustrates the principle of increasing the pixelfrequency by concealing the transient response time to on asettling-segment that is advanced in time. FIG. 6 shows properties ofthe pixel frequency and frame frequency for the conventional sensorarray architecture and the sensor array architecture according to anexample embodiment of the invention, both having N positions with #_(C)column/signal lines and #_(R) row/selection lines, and for a scaledarray having S#_(C) column/signal lines and S#_(R) row/selection lines.The parameters relating to the scaled array are identified by a “*”superscript. The array is labeled 600 and the scaled array is labeled601 in FIG. 6.

A biosensor arrangement 700 according to a second example embodiment ofthe invention is described below with reference to FIG. 7. The biosensorarrangement 700 is shown schematically in FIG. 7.

The detection of specific DNA sequences using the biosensor arrangement700 is based on detecting at the individual sensor positionselectrochemically generated electric currents that vary over time. Thenecessary read-out speed is thus set by the time constants of theelectrochemical reactions, or specifically by the physical processescorrelated with them (for example diffusion).

Such time constants, which are of the order of 500 ms, are largecompared with the reciprocal frequencies typical in electronics. Onemust also bear in mind, however, that the current signals lie in adynamic range of approximately 1 pA to 100 nA.

An important mechanism determining the speed in electronic circuits isthe fact that a driver current I must transfer the charge in acapacitance C (for example the gate capacitance of a MOS transistor) togive a certain voltage change ΔU. Such charge-transfer operations takeplace, for example, during the transient phases of circuits. The time Atrequired for this is given by Δt=ΔU*C/I. If one considers by way ofexample the lower range of possible sensor currents, for I=1 pa, ΔU=1V,C=1 pF, a time of Δt=1000 ms is already obtained. The capacitance valueused in the example is if anything rather small considering associatedachievable statistical tolerances of switching components in thesub-threshold region.

These estimates show that despite the read-out speed requirements beingapparently quite low at first glance, the DNA sensor array is actually asuitable system to implement the circuit arrangement according to anexample embodiment of the invention.

In the biosensor arrangement 700, a sensor-field area 701 is provided inwhich biosensor elements 702 are arranged in the form of a matrix. Forsimplicity's sake, only one of these biosensor elements 702 is shown inFIG. 7. For a sensor event at the biosensor element 702, a sensorcurrent I_(sensor) occurs that is typically of the order of 1 pA to 100nA. This is amplified using a sensor-field amplifier element 703. Thesensor signal I_(Sensor) can be coupled into the electronic interfacecircuit 313 given suitable switch settings of a row-selection switch 704and a column-selection switch 705.

The electronic interface circuit 313 shown in the example embodiment ofFIG. 7 includes a first interface amplifier element 706 having an inputand two outputs. The sensor signal I_(Sensor) of the biosensor element702 can be supplied to the input. A first output of the first interfaceamplifier element 706 is connected to an input of a second interfaceamplifier element 707. A second output of the first interface amplifierelement 706 is connected to a first input of a comparator 712, whosesecond input is connected to a reference current source 711 forsupplying a reference current I_(Ref). The output of the comparator 712is connected to an input of a latch 713, the latch 713 being controlledby a control signal Comp_Valid.

The output signal from the latch 713 controls the second interfaceamplifier element 707 and is supplied to a first input of a transferelement 709. An output of the second interface amplifier element 707 isconnected to an input of an analog-to-digital converter 708, whoseoutput is connected to a second input of the transfer element 709. Thetransfer element 709 is controlled by a control signal Data_Valid. Anoutput of the transfer element 709 is connected to an input of an outputregister 710.

FIG. 7 shows schematically a data path for the read-out of theelectronic DNA sensor array 700. The sensor-field area 701 and theinterface circuit 313 are shown separately as blocks. In thesensor-field area 701 the biosensor element 702 is shown by way ofexample, which can be connected via the row-selection andcolumn-selection switches 704, 705 to the interface circuit 313. Theprimary sensor signal I_(Sensor) is already pre-amplified in thebiosensor element 702 by a first gain factor A₀ using the sensor-fieldamplifier element 703.

In the interface circuit block 313, the signal is then post-amplified bya gain factor A1 using the first interface amplifier element 706, andduplicated. Since it is not always advantageous or may be difficult todesign one analog-to-digital converter 708 for the whole dynamic rangedefined by the primary sensor signal I_(Sensor), range adjustment isprovided in the example of FIG. 7. This allows the five decades of theprimary sensor signal (1 pA to 100 nA) to be mapped onto a suitablynarrow dynamic range at the input of the analog-to-digital converter708. This is done by a copy of the sensor signal following amplificationA1 being supplied to a comparator circuit 712 (or a plurality ofcomparator circuits) where it is compared with a reference currentI_(Ref).

Range-selection bits are obtained as a result of this operation, whichundergo configurable post-amplification A2 implemented by the secondinterface amplifier element 707. The result of the A/D conversion usingthe analog-to-digital converter 708 is written, together with therange-selection bits, to an output register 710 from where it can beread out. In order to keep necessary transient response times short, thedigital data is latched using the control signals Comp_Valid,Data_Valid.

A sensor arrangement 800 according to a third example embodiment of theinvention is described below with reference to FIG. 8, in which theinterface circuit 801 is implemented in a similar way to that shown inFIG. 7.

In FIG. 8, a column line 305 of a read-selected sensor element 302 b isconnected to an input of the first interface amplifier element 706,which performs the functions of the buffer unit 307 shown in FIG. 3A.The first interface amplifier element 706 has two outputs. A firstoutput of the first interface amplifier element 706 is connected to aninput of the second interface amplifier element 707, whose output isconnected to an input of the analog-to-digital converter 708. An outputof the analog-to-digital converter 708 is connected to an input of anoutput block 802.

In addition, a second output of the first interface amplifier element706 is connected to a first input of the comparator 712, whose secondinput is connected to the reference current source I_(Ref)(1−n) 711. Theoutput of the comparator 712 is connected to a control input (forproviding a control signal) of the second interface amplifier element707, and is connected to the output block 802.

FIG. 8 shows an implementation corresponding to the circuit architectureaccording to an example embodiment of the invention, where thepost-amplifier stage A1 706 is arranged in a stage between thepre-decoder 310 and the signal decoder 803.

A biosensor arrangement 900 according to a fourth example embodiment ofthe invention is described below with reference to FIG. 9.

The biosensor arrangement 900 shown in FIG. 9 differs from the biosensorarrangement 800 shown in FIG. 8 in that the electronic interface circuit901 in FIG. 9 is provided in a modified form compared with FIG. 8. InFIG. 9, reference current sources 711 and comparators 712 are moved intothe stage between signal decoder 803 and pre-decoder 310. By movingfunctions into the stage between components 310 and 803, the read-outspeed is further increased by such components being included in theconcealed transient behavior.

A biosensor arrangement 1000 according to a fifth example embodiment ofthe invention is described below with reference to FIG. 10.

The biosensor arrangement 1000 shown in FIG. 10 differs from thebiosensor arrangement 900 shown in FIG. 9 in that, in addition to thecomponents of the electronic interface circuit 1001 already moved inFIG. 9 into the stage between components 310 and 803, in FIG. 10 thesecond interface amplifier elements 707 are also connected betweencomponents 310 and 803. This further increases the read-out speed.

It should be noted that in a similar way to that shown in FIG. 9 andFIG. 10, other components of the electronic interface circuit can alsobe moved into the stage between signal decoder 803 and pre-decoder 310.

Example embodiments being thus described, it will be obvious that thesame may be varied in many ways. Such variations are not to be regardedas a departure from the spirit and scope of the present invention, andall such modifications as would be obvious to one skilled in the art areintended to be included within the scope of the following claims.

The following publications are cited in this document:

[1] Thewes, R et al. “Sensor arrays for fully electronic DNA detectionon CMOS”, in Proc. ISSCC 2002, p. 350

[2] DE 102 47 889 A1

[3] EP 1 217 364 A2

[4] WO 01/75462 A1

[5] DE 101 33 363 A1

LIST OF REFERENCE NUMERALS

-   100 sensor arrangement-   101 substrate-   102 sensor element-   102 a selected sensor element-   103 row lines-   104 column lines-   105 row decoder-   106 column decoder-   107 electronic interface circuit-   108 address generator-   109 sensor field-   110 switch element-   111 selection switch-   150 sensor arrangement-   151 first amplifier-   152 reference current source-   153 comparator-   154 second amplifier-   155 analog-to-digital converter-   156 output unit-   200 sensor element-   200 a selected sensor element-   201 row lines-   202 column lines-   203 selected selection-line group-   204 selected signal-line group-   205 pre-decoder-   206 buffer unit-   207 switch element-   300 sensor arrangement-   301 silicon substrate-   302 sensor elements-   302 a settling-selected sensor element-   302 b read-selected sensor element-   303 selection lines-   304 selected selection-line group-   305 signal lines-   306 selected signal-line group-   307 buffer unit-   308 selection unit-   309 signal unit-   310 pre-decoder-   311 first switch elements-   312 signal decoder-   313 electronic interface circuit-   314 address generator-   315 second switch element-   400 function block-   401 a first signal line-   401 b second signal line-   402 first switching transistor-   403 second switching transistor-   404 third switching transistor-   405 pointer circuit-   406 input-   407 output-   408 flip-flop-   409 fourth switching transistor-   410 ground potential-   500 conventional implementation-   501 implementation according to an example embodiment of the    invention-   600 array-   601 scaled array-   700 biosensor arrangement-   701 sensor-field area-   702 biosensor element-   703 sensor-field amplifier element-   704 line-selection switch-   705 column-selection switch-   706 first interface amplifier element-   707 second interface amplifier element-   708 analog-to-digital converter-   709 transfer element-   710 output register-   711 reference current source-   712 comparator-   713 latch-   800 biosensor arrangement-   801 electronic interface circuit-   802 output block-   803 signal decoder-   900 biosensor arrangement-   901 electronic interface circuit-   1000 biosensor arrangement-   1001 electronic interface circuit

1. A circuit arrangement, comprising: a substrate; a plurality offunctional units arranged on the substrate; a plurality ofselection-line groups, each selection-line group having at least twoselection lines, each being connectable to at least two of thefunctional units; a plurality of signal-line groups, each signal-linegroup having at least two signal lines, each being connectable to atleast two of the functional units; a buffer unit for each signal-linegroup; a selection unit connected to the selection-line groups,configured such that by applying a selection signal to the selectionlines of a selection-line group to be selected, the functional unitsconnected to the selection lines of the selected selection-line groupare connected to the associated signal lines; a signal unit connected tothe signal lines, configured such that it selects one, and only one, ofthe signal-line groups at a time in such a way that, of those functionalunits that belong both to the selected selection-line group and to theselected signal-line group, one, and only one, functional unit isselected at a time for signal transfer between this functional unit andthe signal unit; of those functional units that belong both to theselected selection-line group and to an unselected signal-line group, itconnects one, and only one, functional unit at a time to the associatedbuffer unit, thereby allowing this functional unit to settle.
 2. Thecircuit arrangement as claimed in claim 1, wherein each selection-linegroup comprises exactly two selection lines.
 3. The circuit arrangementas claimed in claim 1, wherein each signal-line group comprises exactlytwo signal lines.
 4. The circuit arrangement as claimed in claim 1,wherein the circuit arrangement is configured as a monolithicallyintegrated circuit arrangement.
 5. The circuit arrangement as claimed inclaim 1, wherein the functional units are sensor fields and configuredsuch that by way of signal transfer between the currently selectedfunctional unit and the signal unit, a sensor signal is readable outfrom the selected functional unit implemented as a sensor field.
 6. Thecircuit arrangement as claimed in claim 1, wherein the circuitarrangement is configured as a biosensor arrangement.
 7. The circuitarrangement as claimed in claim 1, wherein the functional units arememory cells and are configured such that by way of signal transferbetween the currently selected functional unit and the signal unit, aninformation signal is readable out from the selected functional unitconfigured as a memory cell.
 8. The circuit arrangement as claimed inclaim 1, wherein the functional units are playback fields and areconfigured such that, by way of signal transfer between the currentlyselected functional unit and the signal unit, a playback signal isprovidable from the selected functional unit configured as a playbackfield.
 9. The circuit arrangement as claimed in claim 1, wherein thecircuit arrangement is configured as a display arrangement.
 10. Thecircuit arrangement as claimed in claim 1, further comprising anamplifier unit, useable to amplify a signal provided by the selectedfunctional unit of the signal unit.
 11. The circuit arrangement asclaimed in claim 1, further comprising a signal processing sub-circuitfor processing a signal to be transferred, where said signal processingsub-circuit is contained at least partially in a respective buffer unitof a respective signal-line group.
 12. The circuit arrangement asclaimed in claim 2, wherein each signal-line group comprises exactly twosignal lines.
 13. The circuit arrangement as claimed in claim 2, whereinthe circuit arrangement is configured as a monolithically integratedcircuit arrangement.
 14. The circuit arrangement as claimed in claim 3,wherein the circuit arrangement is configured as a monolithicallyintegrated circuit arrangement.
 15. The circuit arrangement as claimedin claim 2, wherein the circuit arrangement is configured as a displayarrangement.
 16. The circuit arrangement as claimed in claim 8, whereinthe circuit arrangement is configured as a display arrangement.
 17. Thecircuit arrangement as claimed in claim 2, wherein the functional unitsare sensor fields and configured such that by way of signal transferbetween the currently selected functional unit and the signal unit, asensor signal is readable out from the selected functional unitimplemented as a sensor field.
 18. The circuit arrangement as claimed inclaim 3, wherein the functional units are sensor fields and configuredsuch that by way of signal transfer between the currently selectedfunctional unit and the signal unit, a sensor signal is readable outfrom the selected functional unit implemented as a sensor field.
 19. Thecircuit arrangement as claimed in claim 4, wherein the functional unitsare sensor fields and configured such that by way of signal transferbetween the currently selected functional unit and the signal unit, asensor signal is readable out from the selected functional unitimplemented as a sensor field.